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Samsung debuts new 7,200 Mbps DRAM module in a notable memory innovation for the data centre

South Korean memory giant touts 13% efficiency gains, greater speeds.

Samsung is gearing up to start shipping a new generation of memory chips, with customers already sampling the industry’s first 512GB DDR5 module, which is capable of up to 7,200 megabits per second (Mbps) and fabbed using High-K Metal Gate process technology, the South Korean conglomerate said March 25.

Samsung first used the HKMG process in its GDDR6 memory in 2018 -- an industry first. Bringing it along the value chain to its DDR5 module Samsung is eyeing real performance boosts. (The new modules will also use approximately 13% less power; a key win for datacenters where energy efficiency is critical.)

DRAM remains a key building block in everything from servers to smartphones.

The new DDR5 -– short for Double Data Rate 5 – specification is an emerging DRAM standard; designed to ensure that the compute-intensive applications fuelling processor core count growth will not be bandwidth-starved by existing DRAM technology.

Samsung has said it expects the transition to DDR5 to begin later in calendar 2021. Support for the new memory standard will arrive with Intel Corp.’s upcoming "Sapphire Rapids" Xeon processors. Samsung has sent samples to Intel, AMD, and major data centre platform providers.

The new memory modules -- which Samsung said will "accelerate AI/ML, exascale computing, analytics, networking, and other data-intensive workloads" -- feature the HKMG technology traditionally used in logic semiconductors. This replaces silicon dioxide with highly conductive metals to reduce energy leakage.

“Samsung is the only semiconductor company with... the expertise to incorporate HKMG cutting-edge logic technology into memory product development,” said Young-Soo Sohn, DRAM VP at Samsung Electronics.

They added: “By bringing this type of process innovation to DRAM manufacturing, we are able to offer our customers high-performance, yet energy-efficient memory solutions to power the computers needed for medical research, financial markets, autonomous driving, smart cities and beyond.”

The company cited support from Intel in its release: "As the amount of data to be moved, stored and processed increases exponentially, the transition to DDR5 comes at a critical inflection point for cloud datacenters, networks and edge deployments,” said Carolyn Duran, Vice President and GM of Memory and IO Technology at Intel.

She added: “Intel’s engineering teams closely partner with memory leaders like Samsung to deliver fast, power-efficient DDR5 memory that is performance-optimized and compatible with our upcoming Intel Xeon Scalable processors, code-named Sapphire Rapids.”

By tapping through-silicon via (TSV) technology (an approach that involves making a hole in a silicon (Si) substrate that is filled with a conducting material to allow 3D electrical routing; facilitating the stacking of chips) Samsung’s DDR5 stacks eight layers of 16Gb DRAM chips to offer the largest capacity of 512GB. TSV was first utilized in DRAM in 2014 when Samsung introduced server modules with capacities up to 256GB.

Speaking to The Stack's founder Ed Targett last year, Micron's Jim Jardine noted that "there are a lot of architectural features that exist in DDR5 that will really take the performance level up, not only from a data rate perspective… but if you think about how data traverses across a data bus, the efficiency with which that is done."

Samsung rival Micron said it had "been able to accomplish that through the inclusion of a couple of really interesting features that depart from the DDR4 spec. The first of those is the burst length: we’re basically putting more data on a single burst than existed in DDR4. We’re also looking at a lot better concurrency within the DDR5 chip itself. [With] significantly larger numbers of banks, when doing bank refresh  — and of course, when you’re refreshing DRAM you’re not writing to it or reading from it — we can actually target those refreshes on a per bank basis; so while you’re refreshing one bank, you can access data from another bank.

Jardine added: "We also do some tricks… with adding things like on-die ECC and relaxing some of the timing parameters that enables that. It really is a technology that addresses a lot of the performance challenges posed by the server system [in the face of] insatiable appetite for more and more data. And it does so just much more efficiently. And we we we get scaling runway to boot. In a nutshell, that’s what DDR5 from a feature set perspective."

Samsung's pricing information was not publicly disclosed. The Stack has asked for more details.