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Intel turns to TSMC, Arm, for new graphics, data centre chips

Hyperscaler collaboration results in new Arm-based chipset.

There were two guest stars of Intel's Architecture Day this week and they were Taiwan's TSMC and the UK's Arm -- with the former set to manufacture "significant elements" of Intel's new GPU semiconductors and the latter unexpectedly making a showing at the heart of Intel's new Infrastructure Processing Unit (IPU).

As Intel pulled the dust covers off two new generations of x86 core architectures and teased a host of other optimisations across its portfolio -- in what it described as its "biggest architectural shift in a generation" -- executives acknowledged that "significant elements" of some of the new chips will be manufactured externally "using TSMC’s N6 and N5 [5nm] process technologies", as Intel ramps up its use of external fabs.

(Taiwanese fab giant TSMC's 5nm N5 entered volume production in the second quarter of 2020. Intel's Stuart Pann, a senior VP in its Corporate Planning Group, explained the relationship in a dedicated blog.)

TSMC was not the only third-party to benefit from Intel's ongoing metamorphosis under its new CEO. The company is also shipping a new data centre-focussed "IPU" chipset, designed of offload some of the nuts-and-bolts workloads that go into keeping a data center running efficiently and securely, so that more server CPU can be rented out to cloud customers.  Somewhat unexpectedly, it's built on Arm Neoverse N1 cores.

Offloading work from the CPU

Among broad promises of faster and more energy-efficient compute spanning the gamut of most conceivable use cases and chip combinations, was the notable new Infrastructure Processing Unit, dubbed "Mount Evans".

This is Intel's first dedicated ASIC-based IPU and has been designed with the aim of letting cloud service providers (CSPs) optimise data centre revenue by offloading infrastructure tasks from CPUs to IPUs.

"Make no mistake, this will change how data centers will be architected for both hyperscale and enterprise alike. CPUs are for tenants, CSP code runs on the IPU" said Intel's data platforms group CTO Guido Appenzeller.

Mount Evans has been "architected and developed hand-in-hand with a top cloud service provider" Intel said.

It implements a hardware accelerated NVMe storage interface for "high-performance network and storage virtualization offload" and offers a programmable packet processing engine enabling use cases like firewalls and virtual routing, as the inefficiency of how data centres are set up becomes a growing area of focus for many.

(NVIDIA's Jensen Huang recently called attention to the fact that "probably half of the CPU cores inside the data center are not running applications", noting on an earnings call that "that’s kind of strange because you created the data center to run services and applications, which is the only thing that makes money… The other half of the computing is completely soaked up running the software-defined data center, just to provide for those applications" he said, adding that "you fundamentally want to change the architecture as a result of that; to offload that software-defined virtualisation and the infrastructure operating system, and the security services to accelerate it… to take that application and software and accelerate it using a form of accelerated computing.")

New Intel architecture: x86 cores revamped

Raja Koduri, Intel SVP, displays a wafer with Intel Arc graphics hardware

Revealed in some detail were two new x86 cores, "Efficient-core" and "Performance-core". The "Efficient-core" microarchitecture, previously codenamed "Gracemont" has been designed for througput efficiency, Intel said, with the ability to "run at low voltage to reduce overall power consumption, while creating the power headroom to operate at higher frequencies." Performance-core meanwhile features more execution ports, more decoders, bigger physical registry files, better branch prediction acuracy, and "overall Geomean improvement of ~19% across a wide range of workloads over current 11th Gen Intel Core processor architecture (Cypress Cove)."

More details on both here. (Not all observers were happy with the level of architectural detail provided, with presentations rich with graphic visualisations but no true detailed architectural illustrations... )

You can watch more here.

The company also unveiled a new scheduling technology called "Intel Thread Director", which -- built directly into the hardware -- provides low-level telemetry on the state of the core and the instruction mix of the thread, letting the OS place the right thread on either big or little core. (Only compatible with Windows 11).

A "software-first" approach to graphics chip optimisation meanwhile has seen Intel complete a "a re-architecture of core graphics driver components, specifically the memory manager and compiler" has seen it improve game load times by 25%.

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